I started by laying down a continuous bead of solder paste, then used the hot air iron on it, then used desoldering braid to clean up any bridges. I used my Aoyue 861A++ rework station to do the soldering. The pins are spaced relatively closely together, so it can be a bit of a beast for someone who is not familiar with SMD work. They are about eight bucks each, and I’d suggest ordering a spare just in case there are any mishaps while soldering it. The CompactFlash socket itself is a surface mount part, digikey part number 3M155880-ND. Until I figure out why, you should assume that IC1 needs to be populated, and the two jumpers to the right of IC1 removed. I haven’t had time to research why yet, and I’m guess it’s either some quirk of timing or some quirk of signal quality. Turns out I was wrong, and CP/M became unstable when reading large files. In fact, I originally wrote up this blog post thinking that approach was working and IC1 could safely be left out. I added some jumpers that supplied RD and WR instead.
I thought I was going to be clever, and omit the OR gate (IC1 in the schematic) that generated IORD and IOWR signals by combining RD/IOREQ and WR/IOREQ. Rc2014 compactflash board, with card installed Hardware ImplementationĪ picture of my prototype is shown below: This also seems to serve some kind of purpose in the master/slave protocol. DASP can be used to implementing a busy LED that will show you when the drive is busy. I’m not sure exactly what that’s for, other than it’s something to do with master/slave mode and we’ve pulled it to 5V. REG and /WE aren’t used in True IDE mode and are pulled to 5V. CSEL has something to do with master/slave cable-select. ATASEL forces the compactflash into True ATA mode.
A03-A10 are addressing pins that we don’t need for 8-bit mode. There are also a number of pins that I tied to ground. Two gates of IC1 are unused and their inputs are grounded. Since IOREQ, RD, and RW are active low, ORing IOREQ and RD is an effective way to generate an active low signal that is only low if both IOREQ and RD are both low. IC1 is a quad OR gate that combines IOREQ and RD to form IORD and combines IOREQ and WR to form IOWR. There’s a /RESET pin, which we hook up to the same reset line that drives the rest of the RC2014.
There are read and write pins, /IORD and /IOWR that are connected to an OR gate that combines the Z80’s IOREQ signal with the Z80’s RD and WR signals. This allows us to select any of eight registers on the compactflash card, which are all the registers we need to implement the 8-bit interface. Either data pins are connected from the Z80 to the CF dard, D0-D8. We don’t need those, so /CS1 is tied to +5V. The compactflash also has a secondary bank, selectable by /CS1. The 74HCT138’s output is tied to the /CS0 pin of the compact flash card, and is used as chip select for the primary bank of compactflash card registers. There’s really no good reason not to jumper it that way. This allows you to set the 74HCT138 be active for only 10h of address space instead of 20h of address space like my other boards. There’s a Jumper, JP3, that can be used to connect A4 to one of the active-low inputs of the 74HCT138. In my example code, I have placed it at E0. This allows us to put the CompactFlash card on any of eight addresses: 00, 20, 40, 60, 80, A0, C0, or E0. As you can see, we have the typical 74HCT138N for address decoding.
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